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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 00:57:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 00:57:12 +0100 |
| commit | 3fe2441185057a5d563fb32157f52a7b6c4205fd (patch) | |
| tree | 9ddc82b0df143a09c15b7c3b4c848720f19a8c53 /README | |
| parent | b59bb8a528bf4fcf764016e61bf6a59239f35b86 (diff) | |
| download | yosys-3fe2441185057a5d563fb32157f52a7b6c4205fd.tar.gz yosys-3fe2441185057a5d563fb32157f52a7b6c4205fd.tar.bz2 yosys-3fe2441185057a5d563fb32157f52a7b6c4205fd.zip | |
Minor README changes
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -295,7 +295,7 @@ Verilog Attributes and non-standard features by adding an empty {* *} statement.) - Modules can be declared with "module mod_name(...);" (with three dots - instead of a list of moudle ports). With this syntax it is sufficient + instead of a list of module ports). With this syntax it is sufficient to simply declare a module port as 'input' or 'output' in the module body. @@ -360,8 +360,7 @@ from SystemVerilog: - The "assert" statement from SystemVerilog is supported in its most basic form. In module context: "assert property (<expression>);" and within an - always block: "assert(<expression>);". It is transformed to a $assert cell - that is supported by the "sat" and "write_btor" commands. + always block: "assert(<expression>);". It is transformed to a $assert cell. - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. |