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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-25 12:46:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-25 12:46:00 +0100 |
| commit | 3fe18c26cd020b31012e465c5a8b1db0abe64182 (patch) | |
| tree | d4cb5d1911d0a78c278b0fb5ed391aa18f76ea25 /README | |
| parent | 9ae21263f0de0c0011c7de290af3600ddeb51a34 (diff) | |
| download | yosys-3fe18c26cd020b31012e465c5a8b1db0abe64182.tar.gz yosys-3fe18c26cd020b31012e465c5a8b1db0abe64182.tar.bz2 yosys-3fe18c26cd020b31012e465c5a8b1db0abe64182.zip | |
Added "keep_hierarchy" attribute
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -288,6 +288,9 @@ Verilog Attributes and non-standard features Setting the "keep" attribute on a module has the same effect as setting it on all instances of the module. +- The "keep_hierarchy" attribute on cells and modules keeps the "flatten" + command from flattening the indicated cells and modules. + - The "init" attribute on wires is set by the frontend when a register is initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis to add the necessary reset logic. |