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| author | whitequark <whitequark@whitequark.org> | 2020-06-04 10:46:54 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2020-06-08 20:19:41 +0000 |
| commit | fbb346ea91a04f2feaf6fa96770fe0cd57020e75 (patch) | |
| tree | 9cf9e3b9020ae24cc9f8219f9b985c8e3589f7a1 /README.md | |
| parent | 8d821dbbdb3ba68d4cd0fdb0d5857e77725275b9 (diff) | |
| download | yosys-fbb346ea91a04f2feaf6fa96770fe0cd57020e75.tar.gz yosys-fbb346ea91a04f2feaf6fa96770fe0cd57020e75.tar.bz2 yosys-fbb346ea91a04f2feaf6fa96770fe0cd57020e75.zip | |
flatten: preserve original object names via hdlname attribute.
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -309,7 +309,9 @@ Verilog Attributes and non-standard features that have ports with a width that depends on a parameter. - The ``hdlname`` attribute is used by some passes to document the original - (HDL) name of a module when renaming a module. + (HDL) name of a module when renaming a module. It should contain a single + name, or, when describing a hierarchical name in a flattened design, multiple + names separated by a single space character. - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that |