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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
| commit | e84cedfae4211244da45ef51a84213874579117e (patch) | |
| tree | fb0a14f4c06675a7d3dbb5a1f22d386402e22d0b /README.md | |
| parent | 3c6a566d865e3d70f8793225a6d211ce3d6246a1 (diff) | |
| parent | e46e8753c84ee83f871d5ce116ce4c08dd49a031 (diff) | |
| download | yosys-e84cedfae4211244da45ef51a84213874579117e.tar.gz yosys-e84cedfae4211244da45ef51a84213874579117e.tar.bz2 yosys-e84cedfae4211244da45ef51a84213874579117e.zip | |
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -510,6 +510,8 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- typedefs are supported (including inside packages) + - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. |