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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:24:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:24:50 -0700 |
| commit | a3371e118b05eb9bd5dddb1c20758674ae50a803 (patch) | |
| tree | 2293da584bc545d2b04948e2f5e28aad2d8b0cea /README.md | |
| parent | e3f20b17afce26f08b277b757e32c33a473a8571 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.tar.gz yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.tar.bz2 yosys-a3371e118b05eb9bd5dddb1c20758674ae50a803.zip | |
Merge branch 'master' into map_cells_before_map_luts
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 8 |
1 files changed, 6 insertions, 2 deletions
@@ -312,10 +312,14 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``whitebox`` attribute on modules triggers the same behavior as + ``blackbox``, but is for whitebox modules, i.e. library modules that + contain a behavioral model of the cell type. + +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should |