diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-09-05 18:10:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 18:10:40 +0200 |
| commit | 82784c279ded1659c882d3385cbd189171c1051a (patch) | |
| tree | ee5fd48c587aedf4e0b41c24d153b3608e984128 /README.md | |
| parent | 8d9196066370b156ae2beefed5aa2da545255e4c (diff) | |
| parent | 71d355560e718147ac9ab769363c6a2b069fd209 (diff) | |
| download | yosys-82784c279ded1659c882d3385cbd189171c1051a.tar.gz yosys-82784c279ded1659c882d3385cbd189171c1051a.tar.bz2 yosys-82784c279ded1659c882d3385cbd189171c1051a.zip | |
Merge pull request #1330 from YosysHQ/clifford/fix1145
Add flatten handling of pre-existing wires as created by interfaces
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -332,6 +332,10 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in ``-pwires`` mode). +- Wires marked with the ``hierconn`` attribute are connected to wires with the + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. + - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` from inserting another clock buffer on a net driven by such output. |