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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:44:42 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:44:42 -0700 |
| commit | 699d8e393953a3e5f0c35afec54464e6810f8f1d (patch) | |
| tree | 4edf4b25dd3c9f8eaf1dad737baa49a04f78ec3f /README.md | |
| parent | 75d92fb590b190e0da43e99853f839b7afb10f83 (diff) | |
| parent | 0067dc44f3928833eede2b9bb40260be78e11a93 (diff) | |
| download | yosys-699d8e393953a3e5f0c35afec54464e6810f8f1d.tar.gz yosys-699d8e393953a3e5f0c35afec54464e6810f8f1d.tar.bz2 yosys-699d8e393953a3e5f0c35afec54464e6810f8f1d.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -350,6 +350,14 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in -pwires mode). + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |