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| author | whitequark <whitequark@whitequark.org> | 2020-04-15 14:16:50 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-15 14:16:50 +0000 |
| commit | 2d436bc4f1f3ca574a89312caf0bf94b81b37f7a (patch) | |
| tree | 8d39249ab05067b73235e2d03ae0ef2aa0adabe9 /README.md | |
| parent | 43cc6bd8a10b47759f4d0d1916d3b7ad108e4486 (diff) | |
| parent | 2106f78bb14eab6c234a0a367ec32ff6680fc6d9 (diff) | |
| download | yosys-2d436bc4f1f3ca574a89312caf0bf94b81b37f7a.tar.gz yosys-2d436bc4f1f3ca574a89312caf0bf94b81b37f7a.tar.bz2 yosys-2d436bc4f1f3ca574a89312caf0bf94b81b37f7a.zip | |
Merge pull request #1918 from whitequark/simplify-improve_enum
ast/simplify: improve enum handling
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -443,8 +443,8 @@ Verilog Attributes and non-standard features - The ``wiretype`` attribute is added by the verilog parser for wires of a typedef'd type to indicate the type identifier. -- Various ``enum_{width}_{value}`` attributes are added to wires of an - enumerated type to give a map of possible enum items to their values. +- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type + to give a map of possible enum items to their values. - The ``enum_base_type`` attribute is added to enum items to indicate which enum they belong to (enums -- anonymous and otherwise -- are |