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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-12 14:41:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-12 14:41:34 +0100 |
| commit | 1f2548a564812d55b8263020d5fe9e92368f818e (patch) | |
| tree | c009f74a9620fbae87e519131ec869b1ff1e96f1 /README.md | |
| parent | b9f6ed40b68f3065077267313ecc07c267b43716 (diff) | |
| parent | da65e1e8d9552f64e1e03c08108ca0532719bbfe (diff) | |
| download | yosys-1f2548a564812d55b8263020d5fe9e92368f818e.tar.gz yosys-1f2548a564812d55b8263020d5fe9e92368f818e.tar.bz2 yosys-1f2548a564812d55b8263020d5fe9e92368f818e.zip | |
Merge pull request #802 from whitequark/write_verilog_async_mem_ports
write_verilog: correctly emit asynchronous transparent ports
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