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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
| commit | 0391499e46cd69cf809fe911fa7798b1ae994540 (patch) | |
| tree | 32708f4d4386049a668e9eb4e88be5b4d53bed03 /README.md | |
| parent | fecafb2207efc772fec49b357bc6e20ca6a25aca (diff) | |
| parent | dca45c0888c44857038bd65b6f51f6d9f67b169f (diff) | |
| download | yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.gz yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.bz2 yosys-0391499e46cd69cf809fe911fa7798b1ae994540.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -312,10 +312,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should |