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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-19 12:33:01 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-19 12:33:18 +0200 |
| commit | fe9689c136bc42dbb3ac4e4ecaaa08d7b4721ab4 (patch) | |
| tree | 87b44831dc87c02765f8cfedd6956559681c68ac /Makefile | |
| parent | affed103e0cb4c79afadccdafebc2a0e2a1f3150 (diff) | |
| download | yosys-fe9689c136bc42dbb3ac4e4ecaaa08d7b4721ab4.tar.gz yosys-fe9689c136bc42dbb3ac4e4ecaaa08d7b4721ab4.tar.bz2 yosys-fe9689c136bc42dbb3ac4e4ecaaa08d7b4721ab4.zip | |
Fixed Verific parser error in ice40 cell library
non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions