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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-04 14:44:35 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-04 14:44:35 +0100 |
| commit | f5d23d4c7af33f73b1d9250e458b0932ff7a965b (patch) | |
| tree | 81a73d274f1b7503d8b0be260115d492d400925e /Makefile | |
| parent | d98fe8ce1fbcd5480181ed22d43b850863191033 (diff) | |
| download | yosys-f5d23d4c7af33f73b1d9250e458b0932ff7a965b.tar.gz yosys-f5d23d4c7af33f73b1d9250e458b0932ff7a965b.tar.bz2 yosys-f5d23d4c7af33f73b1d9250e458b0932ff7a965b.zip | |
Update Verific default path
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -357,7 +357,7 @@ endif endif ifeq ($(ENABLE_VERIFIC),1) -VERIFIC_DIR ?= /usr/local/src/verific_lib_eval +VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC ifeq ($(OS), Darwin) |