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author | Clifford Wolf <clifford@clifford.at> | 2016-11-28 14:45:05 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-11-28 14:45:05 +0100 |
commit | c7f6fb6e17dca8171c4ef08b30ae96e2404de78a (patch) | |
tree | 23053b727e76e08ff2c07c060b7cf9a7368954fd /Makefile | |
parent | c17d98f55c51582943b5865008c9477fe1f3e10a (diff) | |
download | yosys-c7f6fb6e17dca8171c4ef08b30ae96e2404de78a.tar.gz yosys-c7f6fb6e17dca8171c4ef08b30ae96e2404de78a.tar.bz2 yosys-c7f6fb6e17dca8171c4ef08b30ae96e2404de78a.zip |
Bugfix in "read_verilog -D NAME=VAL" handling
Diffstat (limited to 'Makefile')
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