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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-12 19:28:14 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-12 19:28:14 +0100 |
| commit | b18f3a297475203420e6cf204bd4b7ea0f61e44f (patch) | |
| tree | bc507c6737c4a2562785fc24993015deca33e7b1 /Makefile | |
| parent | fd3e10c2955242e9d1c5438da84b4a2341e79173 (diff) | |
| download | yosys-b18f3a297475203420e6cf204bd4b7ea0f61e44f.tar.gz yosys-b18f3a297475203420e6cf204bd4b7ea0f61e44f.tar.bz2 yosys-b18f3a297475203420e6cf204bd4b7ea0f61e44f.zip | |
Changes for Verific 3.16_484_32_151112
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -179,7 +179,7 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval -VERIFIC_COMPONENTS ?= verilog vhdl database util containers +VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) endif |