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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-23 14:35:11 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-23 14:35:11 -0700 |
| commit | 93d19dc2fb35335607e67cab8ecf5ebe28268a1f (patch) | |
| tree | 5646e8cce87de4aee65e89297dbc431290f0fe77 /Makefile | |
| parent | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (diff) | |
| download | yosys-93d19dc2fb35335607e67cab8ecf5ebe28268a1f.tar.gz yosys-93d19dc2fb35335607e67cab8ecf5ebe28268a1f.tar.bz2 yosys-93d19dc2fb35335607e67cab8ecf5ebe28268a1f.zip | |
Add support for module instances.
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions