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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-06 07:21:50 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-06 07:21:50 +0100 |
| commit | 910d94b21214b78d841cfb32a724c4f0ea8b365d (patch) | |
| tree | 9361a94c748f3a17ee8d0c7b58bb0d30e4d15527 /Makefile | |
| parent | 1bb728e24fd4e2a2a4025aba43344b1072d92e2e (diff) | |
| download | yosys-910d94b21214b78d841cfb32a724c4f0ea8b365d.tar.gz yosys-910d94b21214b78d841cfb32a724c4f0ea8b365d.tar.bz2 yosys-910d94b21214b78d841cfb32a724c4f0ea8b365d.zip | |
Verific updates
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -357,7 +357,7 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval -VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree +VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC ifeq ($(OS), Darwin) LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz |