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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-05-17 09:33:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-17 09:33:20 +0200 |
| commit | 7c64c707279fd115cc8bc49c92ca69b159aa6866 (patch) | |
| tree | 3fd01238763f9c32d70adc9cbf0f79379bfd394a /Makefile | |
| parent | 98c7804b89f5d384c920fe2280ed33432207f0cb (diff) | |
| parent | 6c6017c97374d0c0c01b87f1ce960ee9316a81b2 (diff) | |
| download | yosys-7c64c707279fd115cc8bc49c92ca69b159aa6866.tar.gz yosys-7c64c707279fd115cc8bc49c92ca69b159aa6866.tar.bz2 yosys-7c64c707279fd115cc8bc49c92ca69b159aa6866.zip | |
Merge pull request #3310 from robinsonb5-PRs/master
Now calls Tcl_Init after creating the interp, fixes clock format.
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions