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| author | whitequark <whitequark@whitequark.org> | 2021-02-05 06:49:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-05 06:49:34 +0000 |
| commit | 3d9898272a5afd60f6080603bf065056d9dca000 (patch) | |
| tree | 600f7d8df8c2d9958053b56f60a3135c712c1e3d /Makefile | |
| parent | 7c6bf42db8cf8e269b04591a80d8e085e072059a (diff) | |
| parent | 98c4feb72ff52f12aadd34b0deccb819d701ff2c (diff) | |
| download | yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.gz yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.bz2 yosys-3d9898272a5afd60f6080603bf065056d9dca000.zip | |
Merge pull request #2572 from antmicro/check-labels
verilog_parser: add label check to gen_block
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions