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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-27 15:55:43 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-27 15:55:43 +0200 |
| commit | 32673edfeae7878a902883575d6b369a5ed8b0a5 (patch) | |
| tree | ac44b0ad0235b5969dbbb5e55e3597a647377327 /Makefile | |
| parent | 8d881826ebeafa524b1ed5e12ebbedb6d6b2a867 (diff) | |
| download | yosys-32673edfeae7878a902883575d6b369a5ed8b0a5.tar.gz yosys-32673edfeae7878a902883575d6b369a5ed8b0a5.tar.bz2 yosys-32673edfeae7878a902883575d6b369a5ed8b0a5.zip | |
Revert "Compile option for enabling async load verific support"
This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 0 insertions, 4 deletions
@@ -20,7 +20,6 @@ ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 DISABLE_VERIFIC_EXTENSIONS := 0 DISABLE_VERIFIC_VHDL := 0 -ENABLE_VERIFIC_ASYNC_LOAD := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 @@ -502,9 +501,6 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog database util containers hier_tree -ifeq ($(ENABLE_VERIFIC_ASYNC_LOAD),1) -CXXFLAGS += -DVERIFIC_ASYNC_LOAD -endif ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT |