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| author | Miodrag Milanović <mmicko@gmail.com> | 2021-10-27 17:20:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-27 17:20:31 +0200 |
| commit | 19c2d6e15d00bccfa5de4dacef3515dbcdbe3154 (patch) | |
| tree | 65409d89c5dd41d8e87596d826c1f9be13d02d59 /Makefile | |
| parent | e14302a3ea2781dca2dfa3933be18c8e26654dce (diff) | |
| parent | f7cc388bb57b66a97ece786697de6c992072a438 (diff) | |
| download | yosys-19c2d6e15d00bccfa5de4dacef3515dbcdbe3154.tar.gz yosys-19c2d6e15d00bccfa5de4dacef3515dbcdbe3154.tar.bz2 yosys-19c2d6e15d00bccfa5de4dacef3515dbcdbe3154.zip | |
Merge pull request #3063 from YosysHQ/micko/verific_aldff
Enable async load dff emit by default in Verific
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 0 insertions, 4 deletions
@@ -20,7 +20,6 @@ ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 DISABLE_VERIFIC_EXTENSIONS := 0 DISABLE_VERIFIC_VHDL := 0 -ENABLE_VERIFIC_ASYNC_LOAD := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 @@ -502,9 +501,6 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog database util containers hier_tree -ifeq ($(ENABLE_VERIFIC_ASYNC_LOAD),1) -CXXFLAGS += -DVERIFIC_ASYNC_LOAD -endif ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT |