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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 10:02:58 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-10-20 10:02:58 +0200 |
| commit | 17269ae59bda6bcf60dbc9ad9d00afc69aa05499 (patch) | |
| tree | 9aac977e351266c61b85867f180d8064c6826af4 /Makefile | |
| parent | 69b2b13ddd98e059f75911fef13718cca23002e3 (diff) | |
| download | yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.tar.gz yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.tar.bz2 yosys-17269ae59bda6bcf60dbc9ad9d00afc69aa05499.zip | |
Option to disable verific VHDL support
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -19,6 +19,7 @@ ENABLE_EDITLINE := 0 ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 DISABLE_VERIFIC_EXTENSIONS := 0 +DISABLE_VERIFIC_VHDL := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 @@ -500,6 +501,10 @@ endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree +ifneq ($(DISABLE_VERIFIC_VHDL),1) +VERIFIC_COMPONENTS += vhdl +CXXFLAGS += -DVERIFIC_VHDL_SUPPORT +endif ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1) VERIFIC_COMPONENTS += extensions CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS |