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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:11:13 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 09:11:13 +0200 |
| commit | 0e7901e45cc54a9bf76a86dd58092f310f72c90a (patch) | |
| tree | 171df18646f7576f4c804c83d25bf863edbb25e9 /Makefile | |
| parent | c1dfc7ca963f13d10d4ba211f87bfe09851ae301 (diff) | |
| parent | 71da8363008159fed399ec74318d83e34642d1f2 (diff) | |
| download | yosys-0e7901e45cc54a9bf76a86dd58092f310f72c90a.tar.gz yosys-0e7901e45cc54a9bf76a86dd58092f310f72c90a.tar.bz2 yosys-0e7901e45cc54a9bf76a86dd58092f310f72c90a.zip | |
Merge pull request #941 from Wren6991/sim_lib_io_clke
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
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