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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-07-10 12:51:02 +0200 |
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| committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-07-10 12:51:02 +0200 |
| commit | 0371519c3977fcf4ffc71315cb9e0aae3ee967a2 (patch) | |
| tree | 4bbdb150e8ac7b9a579d13e819178d65b15fad13 /Makefile | |
| parent | e7d3f3cd464fe323872285bed40e6f347683147b (diff) | |
| download | yosys-0371519c3977fcf4ffc71315cb9e0aae3ee967a2.tar.gz yosys-0371519c3977fcf4ffc71315cb9e0aae3ee967a2.tar.bz2 yosys-0371519c3977fcf4ffc71315cb9e0aae3ee967a2.zip | |
Added Monitor class that can monitor all changes in a Design or in a Module
Diffstat (limited to 'Makefile')
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