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author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-25 22:47:46 +0800 |
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committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-25 22:47:46 +0800 |
commit | 1b369442995ea3f83d0d0445bb34c8f8115c10a3 (patch) | |
tree | 49d7c8584cdc50641ac9f4ddcd4b7fec87e4eb7f /CodeOfConduct | |
parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
download | yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.tar.gz yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.tar.bz2 yosys-1b369442995ea3f83d0d0445bb34c8f8115c10a3.zip |
anlogic: add latch cells
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'CodeOfConduct')
0 files changed, 0 insertions, 0 deletions