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author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-12 17:05:39 +0100 |
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committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-15 17:17:29 +0100 |
commit | a55bf6375b38a955de4589a66e4d2992ac7dd621 (patch) | |
tree | 2f9a517b5eb61dfc37a08a818bdd0214546d96ff /COPYING | |
parent | 3af871f969f7f5bd5201bac17544559671312a6f (diff) | |
download | yosys-a55bf6375b38a955de4589a66e4d2992ac7dd621.tar.gz yosys-a55bf6375b38a955de4589a66e4d2992ac7dd621.tar.bz2 yosys-a55bf6375b38a955de4589a66e4d2992ac7dd621.zip |
proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been
remade as follows:
- now triggered for the last remaining edge trigger after all others
have been converted to async reset, not just when there is only one
sync rule in the first place
- does not require all contained assignments to be constant, as opposed
to a reset conditional — merely const-folds the condition
In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).
Fixes #2656.
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions