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| author | Zachary Snow <zach@zachjs.com> | 2021-02-06 23:54:17 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-07 11:48:39 -0500 |
| commit | 1d5f3fe5064146955dafdabafe7180ff79c95d08 (patch) | |
| tree | ccc9c6a40e9ea885b693f6c2e51202f4217453d2 /CODEOWNERS | |
| parent | eff18a2b1519428b11400979f116342086c13e13 (diff) | |
| download | yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.tar.gz yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.tar.bz2 yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.zip | |
verlog: allow shadowing module ports within generate blocks
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
Diffstat (limited to 'CODEOWNERS')
0 files changed, 0 insertions, 0 deletions