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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
| commit | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (patch) | |
| tree | d1a4bb9dfe62ac911ca4751a98b3b63dba22af40 /CHECKLISTS | |
| parent | 6ca0c569d92883b6eac1725204de90aee4af31bc (diff) | |
| download | yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.gz yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.bz2 yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.zip | |
Renamed "stdcells.v" to "techmap.v"
Diffstat (limited to 'CHECKLISTS')
| -rw-r--r-- | CHECKLISTS | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/CHECKLISTS b/CHECKLISTS index 8a149a539..3a06e61e0 100644 --- a/CHECKLISTS +++ b/CHECKLISTS @@ -124,7 +124,7 @@ Things to do right away: - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells) - Add to InternalCellChecker::check() in kernel/rtlil.cc - Add to techlibs/common/simlib.v - - Add to techlibs/common/stdcells.v + - Add to techlibs/common/techmap.v Things to do after finalizing the cell interface: |