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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:18:01 -0700 |
| commit | f374e0ab7e9a91fa86814b0f750660e92ed16ae6 (patch) | |
| tree | ae525a0ffa0e9588c833cf864f1eea62436afa4f /CHANGELOG | |
| parent | 4e8f0fbce84db96f8cd3d4e1594b30cbc8ec1020 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.gz yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.tar.bz2 yosys-f374e0ab7e9a91fa86814b0f750660e92ed16ae6.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -18,11 +18,12 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "equiv_opt" pass - Added "read_aiger" frontend - Added "shregmap -tech xilinx" + - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) + - Extended "muxcover -mux{4,8,16}=<cost>" - Added "synth -abc9" (experimental) - - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) |