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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 11:39:14 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-17 11:39:14 +0100 |
| commit | e45f62b0c56717a23099425f078d1e56212aa632 (patch) | |
| tree | a87d0ea6125ae7a00210ad890716c4417994bf2c /CHANGELOG | |
| parent | 807b3c769733b8cf07f5b14674df41bd2788e09d (diff) | |
| parent | c245041bfe2ee0d5b5504fa5e9459ac52e836c33 (diff) | |
| download | yosys-e45f62b0c56717a23099425f078d1e56212aa632.tar.gz yosys-e45f62b0c56717a23099425f078d1e56212aa632.tar.bz2 yosys-e45f62b0c56717a23099425f078d1e56212aa632.zip | |
Merge pull request #811 from ucb-bar/firrtlfixes
Update cells supported for verilog to FIRRTL conversion.
Diffstat (limited to 'CHANGELOG')
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