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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-22 13:31:30 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 13:31:30 -0700 |
| commit | d9daf09cf3aab202b6da058c5e959f6375a4541e (patch) | |
| tree | 50f92b27b889077951583496266d214b5e0a30c7 /CHANGELOG | |
| parent | bc98a463a433e5b1553b307301e67e641a148d3c (diff) | |
| parent | ec88129a5cf510afc39ea12efa6059bed3eadfc3 (diff) | |
| download | yosys-d9daf09cf3aab202b6da058c5e959f6375a4541e.tar.gz yosys-d9daf09cf3aab202b6da058c5e959f6375a4541e.tar.bz2 yosys-d9daf09cf3aab202b6da058c5e959f6375a4541e.zip | |
Merge pull request #914 from YosysHQ/xc7srl
synth_xilinx to now infer SRL16E/SRLC32E
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" Yosys 0.7 .. Yosys 0.8 |