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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 17:00:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 17:00:36 -0700 |
| commit | d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2 (patch) | |
| tree | 426c67083254f8eea67464d34747bfb201d9bdb6 /CHANGELOG | |
| parent | 816b5f5891adfa71586991824e9db24e7e73604a (diff) | |
| download | yosys-d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2.tar.gz yosys-d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2.tar.bz2 yosys-d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2.zip | |
Update CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 6 |
1 files changed, 2 insertions, 4 deletions
@@ -16,12 +16,10 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass -<<<<<<< HEAD - - Added "muxpack" pass -======= - Added "read_aiger" frontend ->>>>>>> origin/master + - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - "synth_xilinx" to now infer wide multiplexers Yosys 0.7 .. Yosys 0.8 |