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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
| commit | d54dceb547777ab4b489f66554d4c47e867424f9 (patch) | |
| tree | 8e60c03e2a40891b7a078717b8a3c931feb5ae83 /CHANGELOG | |
| parent | bbf3ad90f59a5b548d263c81ca83ca8f93f1c238 (diff) | |
| parent | 6027549464bf91cee4d4bcbe9586e719dce78c80 (diff) | |
| download | yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.gz yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.bz2 yosys-d54dceb547777ab4b489f66554d4c47e867424f9.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 9 |
1 files changed, 5 insertions, 4 deletions
@@ -18,16 +18,17 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "equiv_opt" pass - Added "shregmap -tech xilinx" - Added "read_aiger" frontend - - Added "shregmap -tech xilinx" + - Added "muxcover -mux{4,8,16}=<cost>" + - Added "muxcover -dmux=<cost>" + - Added "muxcover -nopartial" + - Added "muxpack" pass - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - Added "muxpack" pass - - Extended "muxcover -mux{4,8,16}=<cost>" - - Fixed sign extension of unsized constants with 'bx and 'bz MSB - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) + - Fixed sign extension of unsized constants with 'bx and 'bz MSB Yosys 0.7 .. Yosys 0.8 |