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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
| commit | d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a (patch) | |
| tree | 526c60c70ac41f71eb0c1a0d83f556ce1b35b126 /CHANGELOG | |
| parent | dccd7eb39f897f7fb04b038ee8ac11e676a8ea77 (diff) | |
| parent | 520f1646cf0c0d83603c4bec2f6a37acca1d4960 (diff) | |
| download | yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.gz yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.bz2 yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -50,9 +50,12 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx + - Added support for flip-flops with synchronous reset to synth_xilinx + - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) + - Added "xilinx_dffopt" pass Yosys 0.8 .. Yosys 0.9 ---------------------- |