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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 12:24:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 12:24:25 -0700 |
| commit | cee30deef5f48b97af961ecb6f7194eac14d891c (patch) | |
| tree | c6dd61285a2c482a1371581fead593143f2d3c3a /CHANGELOG | |
| parent | 08139aa53ab2aa7916c9c42fab9bf6261621c265 (diff) | |
| download | yosys-cee30deef5f48b97af961ecb6f7194eac14d891c.tar.gz yosys-cee30deef5f48b97af961ecb6f7194eac14d891c.tar.bz2 yosys-cee30deef5f48b97af961ecb6f7194eac14d891c.zip | |
Mention shregmap -tech xilinx is superseded
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -29,7 +29,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Removed "ice40_unlut" - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - - Removed "shregmap -tech xilinx" + - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") Yosys 0.8 .. Yosys 0.8-dev -------------------------- |