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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-21 06:30:06 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-18 13:43:43 +0100 |
| commit | aff6ad1ce09264fb7fbf43a7456a746a586bea90 (patch) | |
| tree | bc8edef3141b31acac3c5dad428a8ff50f840cc0 /CHANGELOG | |
| parent | 22dd9f107c8986463041709aabcd0c886c87d33f (diff) | |
| download | yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.tar.gz yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.tar.bz2 yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.zip | |
xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -50,6 +50,8 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx + - Added support for flip-flops with synchronous reset to synth_xilinx + - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) |