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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
| commit | 99ff7b5c8c74371841e74d81b7a0d63cd9487e61 (patch) | |
| tree | 72e3b31c807eef5f39c797c8eb3530da98f78980 /CHANGELOG | |
| parent | 31b0dee7f3f12c76b721f2fa8e11c722307abb09 (diff) | |
| parent | 3b8f3a93ada563fbae62772b0bf642bb54170954 (diff) | |
| download | yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.gz yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.bz2 yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.zip | |
Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -23,6 +23,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Extended "muxcover -mux{4,8,16}=<cost>" + - Fixed sign extension of unsized constants with 'bx and 'bz MSB - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) @@ -38,7 +39,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts |