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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-21 10:12:32 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-21 10:12:32 +0200 |
| commit | 86a753cc18f4e85449a93042298a8e4a617c674a (patch) | |
| tree | 0007b998ef3595c9a3ad5323c585fdcd6a809313 /CHANGELOG | |
| parent | c4ea6fff65d6b2e69a31649af7e10b129c6ae0f5 (diff) | |
| parent | 3b8f3a93ada563fbae62772b0bf642bb54170954 (diff) | |
| download | yosys-86a753cc18f4e85449a93042298a8e4a617c674a.tar.gz yosys-86a753cc18f4e85449a93042298a8e4a617c674a.tar.bz2 yosys-86a753cc18f4e85449a93042298a8e4a617c674a.zip | |
Merge pull request #1116 from YosysHQ/eddie/fix1115
Sign extend unsized 'bx and 'bz values
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -19,6 +19,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "read_aiger" frontend - Extended "muxcover -mux{4,8,16}=<cost>" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - Fixed sign extension of unsized constants with 'bx and 'bz MSB Yosys 0.7 .. Yosys 0.8 @@ -32,7 +33,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts |