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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 09:15:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-13 09:15:30 -0700 |
| commit | 7f9d2d18251c3bec667993c744b568bbbe1a75ce (patch) | |
| tree | 581d4e3639a46c76eb44b819304e9220263fccd3 /CHANGELOG | |
| parent | 2052806d3361dca8a866aee0665af223db51bdbd (diff) | |
| download | yosys-7f9d2d18251c3bec667993c744b568bbbe1a75ce.tar.gz yosys-7f9d2d18251c3bec667993c744b568bbbe1a75ce.tar.bz2 yosys-7f9d2d18251c3bec667993c744b568bbbe1a75ce.zip | |
Update CHANGELOG with "synth -abc9"
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |