diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:22:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:22:53 -0700 |
| commit | 7a9031c48ed91de674f4ad1507b1148153930d0d (patch) | |
| tree | 17fe975539c1611c75f733422bb14a4415d659ab /CHANGELOG | |
| parent | 36d94caec169d232e8bf1a668ef9062ab38395ea (diff) | |
| download | yosys-7a9031c48ed91de674f4ad1507b1148153930d0d.tar.gz yosys-7a9031c48ed91de674f4ad1507b1148153930d0d.tar.bz2 yosys-7a9031c48ed91de674f4ad1507b1148153930d0d.zip | |
Add CHANGELOG entry
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "opt_share" pass, run as part of "opt -full" - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping - Removed "ice40_unlut" + - Added "xilinx_srl" for Xilinx shift register extraction + - Removed "shregmap -tech xilinx" Yosys 0.8 .. Yosys 0.8-dev -------------------------- |