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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-07 23:13:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-07 23:13:34 +0200 |
| commit | 7395a8069064c90aa0895607ad45f1165d372684 (patch) | |
| tree | 17db4d2fd97197eb80dc5d2433e39be8f637fafd /CHANGELOG | |
| parent | 6d49145497e48bb063ebbed5164b45569e91b5ca (diff) | |
| parent | f48c6920b7aa777c0c569f444e3db88211835cec (diff) | |
| download | yosys-7395a8069064c90aa0895607ad45f1165d372684.tar.gz yosys-7395a8069064c90aa0895607ad45f1165d372684.tar.bz2 yosys-7395a8069064c90aa0895607ad45f1165d372684.zip | |
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |