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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:20:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:20:46 -0700 |
| commit | 738fdfe8f55e18ac7f315cd68c117eae370004ca (patch) | |
| tree | 534b94c5f56dbe726b4b45f7e5dfd1280ca58312 /CHANGELOG | |
| parent | b2c72f74f00032d1ac5071f8bb32b87c9dc4c23e (diff) | |
| download | yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.tar.gz yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.tar.bz2 yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.zip | |
Remove wide mux inference
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -18,7 +18,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "equiv_opt" pass - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - - "synth_xilinx" to now infer wide multiplexers Yosys 0.7 .. Yosys 0.8 |