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| author | David Shah <dave@ds0.me> | 2020-02-02 18:12:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-02 18:12:28 +0000 |
| commit | 7033503cd9e40e16c11fe6c805a436b0e23989dd (patch) | |
| tree | 23d26103ac47ed62f2d0f805b6677943ef4f1795 /CHANGELOG | |
| parent | 9f5613100b360beb60608df1296ee81dc185e56c (diff) | |
| parent | 0488492ad269df9641ab317eac5568353dd61076 (diff) | |
| download | yosys-7033503cd9e40e16c11fe6c805a436b0e23989dd.tar.gz yosys-7033503cd9e40e16c11fe6c805a436b0e23989dd.tar.bz2 yosys-7033503cd9e40e16c11fe6c805a436b0e23989dd.zip | |
Merge pull request #1516 from YosysHQ/dave/dotstar
sv: Add support for wildcard port connections (.*)
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -55,6 +55,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) + - Added support for SystemVerilog wildcard port connections (.*) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - Added "abc9 -dff" |