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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 15:47:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 15:47:28 -0700 |
| commit | 58f4b106f3b5914fa00edd59bb2df56d9fe2632e (patch) | |
| tree | 2c8a34fc19815adfbf952e93c9726a0318bb5e23 /CHANGELOG | |
| parent | f705f6a0b5d19d38cf41ba5f782847de54110463 (diff) | |
| parent | 2b350401c4577d54c0d460240e2d2847d2eeadc4 (diff) | |
| download | yosys-58f4b106f3b5914fa00edd59bb2df56d9fe2632e.tar.gz yosys-58f4b106f3b5914fa00edd59bb2df56d9fe2632e.tar.bz2 yosys-58f4b106f3b5914fa00edd59bb2df56d9fe2632e.zip | |
Merge branch 'master' into eddie/muxpack
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |