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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-20 20:16:37 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-20 20:16:37 +0200 |
| commit | 545bcb37e8fa569d88374f92aafdcc1004e9b587 (patch) | |
| tree | 8df204605907e01759969afa2386274ea398c620 /CHANGELOG | |
| parent | 541083cf329addb57117618de41697dd010d07cf (diff) | |
| download | yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.tar.gz yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.tar.bz2 yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.zip | |
Allow defining input ports as "input logic" in SystemVerilog
Diffstat (limited to 'CHANGELOG')
0 files changed, 0 insertions, 0 deletions