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| author | Clifford Wolf <clifford@clifford.at> | 2017-04-07 10:01:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-07 10:01:28 +0200 |
| commit | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (patch) | |
| tree | d4a693bbb884f2c6b159d1349f5138c695f67fa4 /CHANGELOG | |
| parent | 7791888703a72880679ebe8ae3bbdc63db8f00e2 (diff) | |
| download | yosys-41d4e91f388f41c97f71567cd5a0f5652a5968fd.tar.gz yosys-41d4e91f388f41c97f71567cd5a0f5652a5968fd.tar.bz2 yosys-41d4e91f388f41c97f71567cd5a0f5652a5968fd.zip | |
Add MAX10 and Cyclone IV items to CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 13 |
1 files changed, 13 insertions, 0 deletions
@@ -3,6 +3,19 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.7 .. Yosys ??? +---------------------- + + * MAX10 and Cyclone IV Support + - Added initial version of metacommand "synth_intel". + - Improved write_verilog command to produce VQM netlist for Quartus Prime. + - Added support for MAX10 FPGA family synthesis. + - Added support for Cyclone IV family synthesis. + - Added example of implementation for DE2i-150 board. + - Added example of implementation for MAX10 development kit. + - Added LFSR example from Asic World. + + Yosys 0.6 .. Yosys 0.7 ---------------------- |