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authorEddie Hung <eddie@fpgeh.com>2019-08-20 12:55:26 -0700
committerGitHub <noreply@github.com>2019-08-20 12:55:26 -0700
commit33960dd3d84b628f6e5de45c112368dc80626457 (patch)
tree71f47cc0dce332fb4e3f15bedfde3327eb0ae60b /CHANGELOG
parent14c03861b6d178c85d6963e673ed51bc142457e1 (diff)
parentd9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (diff)
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
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@@ -14,6 +14,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth -abc9" (experimental)
- Added "script -scriptwire
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
+ - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+ - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+ - Renamed labels in synth_intel (e.g. bram -> map_bram)
+ - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added automatic gzip decompression for frontends
- Added $_NMUX_ cell type
- Added automatic gzip compression (based on filename extension) for backends