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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 19:17:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 19:17:11 -0700 |
| commit | 1d0be89214466aa5120d6fc0e155c6366ae8e802 (patch) | |
| tree | 3db47959c93cc62e1f0fe964d92417d6f93ee1ed /CHANGELOG | |
| parent | 5fa2afc58c9143f08879b9d778d187182968df88 (diff) | |
| download | yosys-1d0be89214466aa5120d6fc0e155c6366ae8e802.tar.gz yosys-1d0be89214466aa5120d6fc0e155c6366ae8e802.tar.bz2 yosys-1d0be89214466aa5120d6fc0e155c6366ae8e802.zip | |
Add write_xaiger into CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -dmux=<cost>" - Added "muxcover -nopartial" - Added "muxpack" pass + - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) |