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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:30 -0700 |
| commit | 13e2e8df11b4af9ce5512508caad793c659b9479 (patch) | |
| tree | 19e86527eb6fb93206f96c193f7272add7db7b26 /CHANGELOG | |
| parent | b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d (diff) | |
| download | yosys-13e2e8df11b4af9ce5512508caad793c659b9479.tar.gz yosys-13e2e8df11b4af9ce5512508caad793c659b9479.tar.bz2 yosys-13e2e8df11b4af9ce5512508caad793c659b9479.zip | |
Update CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -17,12 +17,13 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend + - Added "shregmap -tech xilinx" - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - - "synth_xilinx" to now infer wide multiplexers + - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) + - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) Yosys 0.7 .. Yosys 0.8 |