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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 12:04:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-06 12:04:42 -0700 |
| commit | 030f1d30e9cd04b4412114bdc93a15a39a4597c4 (patch) | |
| tree | c19ab158e5c658cc3dc8839b2cc4b1959fbc9003 /CHANGELOG | |
| parent | b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 (diff) | |
| download | yosys-030f1d30e9cd04b4412114bdc93a15a39a4597c4.tar.gz yosys-030f1d30e9cd04b4412114bdc93a15a39a4597c4.tar.bz2 yosys-030f1d30e9cd04b4412114bdc93a15a39a4597c4.zip | |
Add to CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |