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| author | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:44:16 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:44:16 +0200 |
| commit | ce4a0954bc896eedfc2d87e2c9d2b40f42a101db (patch) | |
| tree | b5bc8a5bbbfd930a9b3a73f862032f1b84935c6c /.travis | |
| parent | 3ef88ffbb2409450d5921938b2b938c4c007e091 (diff) | |
| download | yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.tar.gz yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.tar.bz2 yosys-ce4a0954bc896eedfc2d87e2c9d2b40f42a101db.zip | |
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to '.travis')
0 files changed, 0 insertions, 0 deletions